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기능 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
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COP8SEC5 데이터시트, 핀배열, 회로
July 1999
COP8SE Family
8-Bit CMOS ROM Based and OTP Microcontrollers with
4k Memory and 128 Bytes EERAM
General Description
The COP8SEx5 Family ROM based microcontrollers are
highly integrated COP8Feature core devices with 4k
memory and advanced features including EERAM.
COP8SER7 devices are pin and software compatible (differ-
ent VCC range), 32k OTP (One Time Programmable) ver-
sions for engineering development use with a range of
COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1µs instruction cycle, 128 bytes of EE-
RAM, one multi-function 16-bit timer/counter, idle timer with
MIWU, MICROWIRE/PLUS, serial I/O, crystal or R/C oscil-
lator, two power saving HALT/IDLE modes, Schmitt trigger
inputs, software selectable I/O options, WATCHDOGtimer
and Clock Monitor, Low EMI 2.7V to 5.5V operation, and
16/20 pin packages.
Devices included in this data sheet are:
Device
OSC Memory (bytes) RAM (bytes) EERAM I/O Pins Package
Temperature
COP8SEC5
4k ROM
128 128 bytes 12/16 16/20 SOIC -40 to +85˚C, -40 to +135˚C
COP8SER7-XE xtal 32k OTP EPROM 128 128 bytes 16 20 SOIC -40 to +85˚C, Engineering
COP8SER7-RE R/C 32k OTP EPROM 128 128 bytes 16 20 SOIC -use only
Key Features
n 256 bytes data memory
— 128 bytes RAM
— 128 bytes EERAM
n OTP with security feature (SER7)
n Quiet Design (low radiated emissions)
n Multi-Input Wakeup pins with optional interrupts (8 pins)
n User selectable clock options:
— R/C oscillator
— Crystal oscillator
Other Features
n Fully static CMOS, with low current drain
n Available with Crystal (-XE) or RC (-RE) oscillator
n Two power saving modes: HALT and IDLE
n 1 µs instruction cycle time
n 4k bytes on-board masked ROM or 32k bytes OTP
n Single supply operation: 2.7V — 5.5V
n MICROWIRE/PLUS Serial Peripheral Interface
Compatible
n Nine multi-source vectored interrupts servicing
— EERAM write complete
— External interrupt
— Idle Timer T0
— One Timer (with 2 Interrupts)
— MICROWIRE/PLUS Serial Interface
— Multi-Input Wake Up
— Software Trap
— Default VIS
n Idle Timer with programmable interrupt interval
n One 16 bit timer with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n 8-bit Stack Pointer SP (stack in RAM)
n Two 8-bit Register Indirect Data Memory Pointers
n Versatile instruction set
n True bit manipulation
n Memory mapped I/O
n BCD arithmetic instructions
n WATCHDOG and Clock Monitor logic
n Software selectable I/O options:
— TRI-STATE® Output:
— Push-Pull Output
— Weak Pull Up Input
— High Impedance Input
n Schmitt trigger inputs on ports G and L
n Temperature ranges:
— −40˚C to +85˚C
— −40˚C to +135˚C (SEC5 only)
n Packaging: 16, and 20 SO (SEC5); 20 SO (SER7)
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS, COP8, MICROWIREand WATCHDOGare trademarks of National Semiconductor Corporation.
iceMASTERis a trademark of MetaLink Corporation.
PC® is a registered trademark of International Business Machines Corporation.
© 1999 National Semiconductor Corporation DS100973
www.national.com




COP8SEC5 pdf, 반도체, 판매, 대치품
Connection Diagrams (Continued)
Pinouts for 16-, and 20-Pin Packages
Port
Type
Alt. Fun
L0 I/O MIWU
L1 I/O MIWU
L2 I/O MIWU
L3 I/O MIWU
L4 I/O MIWU
L5 I/O MIWU
L6 I/O MIWU
L7 I/O MIWU
G0 I/O
INT
G1 I/O WDOUT*
G2 I/O T1B
G3 I/O T1A
G4 I/O
SO
G5 I/O
SK
G6 I
SI
G7 I CKO
D0 O
D1 O
D2 O
D3 O
F0 I/O
F1 I/O
F2 I/O
F3 I/O
VCC
GND
CKI I
RESET
I
* G1 operation as WDOUT is controlled by Mask Option.
2.1 Ordering Information
20-Pin SO
7
8
9
10
11
12
13
14
17
18
19
20
1
2
3
4
6
15
5
16
16-Pin SO
7
8
9
10
13
14
15
16
1
2
3
4
6
11
5
12
www.national.com
FIGURE 3. Part Numbering Scheme
4
DS100973-8

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COP8SEC5 전자부품, 판매, 대치품
AC Electrical Characteristics
−40˚C TA +85˚C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
Instruction Cycle Time (tC)
Crystal/Resonator
R/C Oscillator
Frequency Variation (Note 9), (Note 10)
CKI Clock Duty Cycle (Note 9)
4.5V VCC 5.5V
2.7V VCC < 4.5V
4.5V VCC 5.5V
2.7V VCC < 4.5V
4.5V VCC 5.5V
fr = Max
1
2
3
6
45
DC µs
DC µs
DC µs
DC µs
±15 %
55 %
Rise Time (Note 9)
fr = 10 MHz Ext Clock
12 ns
Fall Time (Note 9)
fr = 10 MHz Ext Clock
8 ns
EERAM Write Cycle
7 15 ms
Delay from Power-Up to first EERAM Write
Cycle
65 µs
Output Propagation Delay (Note 8)
tPD1, tPD0
RL = 2.2k, CL = 100
pF
SO, SK
All Others
MICROWIRE Setup Time (tUWS) (Note 12)
MICROWIRE Hold Time (tUWH) (Note 12)
MICROWIRE Output Propagation Delay
(tUPD)(Note 12)
Input Pulse Width (Note 9)
4.5V VCC 5.5V
2.7V VCC < 4.5V
4.5V VCC 5.5V
2.7V VCC < 4.5V
20
56
0.7 µs
1.75 µs
1 µs
2.5 µs
ns
ns
220 ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
1 tC
1 tC
1 tC
1 tC
1 µs
Note 3: tC = Instruction cycle time.
Note 4: Maximum rate of voltage change must be < 0.5 V/ms.
Note 5: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 6: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, G0, and G2–G5 programmed as low out-
puts and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; WATCHDOG and clock monitor disabled. Parameter refers to
HALT mode entered via setting bit 7 of the G Port data register.
Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750(typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
cludes ESD transients.
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter characterized but not tested.
Note 10: Rise times faster than the minimum specification may trigger an internal power-on-reset.
Note 11: Exclusive of R and C variation.
Note 12: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See Figure 4 and the MI-
CROWIRE operation description.
Note 13: COP7SER7 Supply Current during Reset will be somewhat higher.
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