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PDF COP8SEC516M Data sheet ( Hoja de datos )
| Número de pieza | COP8SEC516M | |
| Descripción | 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM | |
| Fabricantes | National Semiconductor | |
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July 1999
COP8SE Family
8-Bit CMOS ROM Based and OTP Microcontrollers with
4k Memory and 128 Bytes EERAM
General Description
The COP8SEx5 Family ROM based microcontrollers are
highly integrated COP8™ Feature core devices with 4k
memory and advanced features including EERAM.
COP8SER7 devices are pin and software compatible (differ-
ent VCC range), 32k OTP (One Time Programmable) ver-
sions for engineering development use with a range of
COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1µs instruction cycle, 128 bytes of EE-
RAM, one multi-function 16-bit timer/counter, idle timer with
MIWU, MICROWIRE/PLUS™, serial I/O, crystal or R/C oscil-
lator, two power saving HALT/IDLE modes, Schmitt trigger
inputs, software selectable I/O options, WATCHDOG™ timer
and Clock Monitor, Low EMI 2.7V to 5.5V operation, and
16/20 pin packages.
Devices included in this data sheet are:
Device
OSC Memory (bytes) RAM (bytes) EERAM I/O Pins Package
Temperature
COP8SEC5
4k ROM
128 128 bytes 12/16 16/20 SOIC -40 to +85˚C, -40 to +135˚C
COP8SER7-XE xtal 32k OTP EPROM 128 128 bytes 16 20 SOIC -40 to +85˚C, Engineering
COP8SER7-RE R/C 32k OTP EPROM 128 128 bytes 16 20 SOIC -use only
Key Features
n 256 bytes data memory
— 128 bytes RAM
— 128 bytes EERAM
n OTP with security feature (SER7)
n Quiet Design (low radiated emissions)
n Multi-Input Wakeup pins with optional interrupts (8 pins)
n User selectable clock options:
— R/C oscillator
— Crystal oscillator
Other Features
n Fully static CMOS, with low current drain
n Available with Crystal (-XE) or RC (-RE) oscillator
n Two power saving modes: HALT and IDLE
n 1 µs instruction cycle time
n 4k bytes on-board masked ROM or 32k bytes OTP
n Single supply operation: 2.7V — 5.5V
n MICROWIRE/PLUS Serial Peripheral Interface
Compatible
n Nine multi-source vectored interrupts servicing
— EERAM write complete
— External interrupt
— Idle Timer T0
— One Timer (with 2 Interrupts)
— MICROWIRE/PLUS Serial Interface
— Multi-Input Wake Up
— Software Trap
— Default VIS
n Idle Timer with programmable interrupt interval
n One 16 bit timer with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n 8-bit Stack Pointer SP (stack in RAM)
n Two 8-bit Register Indirect Data Memory Pointers
n Versatile instruction set
n True bit manipulation
n Memory mapped I/O
n BCD arithmetic instructions
n WATCHDOG and Clock Monitor logic
n Software selectable I/O options:
— TRI-STATE® Output:
— Push-Pull Output
— Weak Pull Up Input
— High Impedance Input
n Schmitt trigger inputs on ports G and L
n Temperature ranges:
— −40˚C to +85˚C
— −40˚C to +135˚C (SEC5 only)
n Packaging: 16, and 20 SO (SEC5); 20 SO (SER7)
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation.
iceMASTER™ is a trademark of MetaLink Corporation.
PC® is a registered trademark of International Business Machines Corporation.
© 1999 National Semiconductor Corporation DS100973
www.national.com
1 page  
3.0 Electrical Characteristics
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
Total Current into VCC
Pin (Source)
Total Current out of
GND Pin (Sink)
7V
−0.3V to VCC +0.3V
80 mA
100 mA
Storage Temperature
Range
−65˚C to +150˚C
ESD Protection Level
2 kV(Human Body Model)
ESD Protection Level
(CKI pin)
150 V(Machine Model)
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
Note 2: The COP8SER7 is for Engineering Development purpose only and
is not recommended for production or pre-production use.
DC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified.
Parameter
Conditions
Operating Voltage
Power Supply Rise Time
Power Supply Ripple (Note 4)
Peak-to-Peak
Supply Current (Note 5)
CKI = 10 MHz
VCC = 5.5V, tC = 1 µs
(SEC5)
(SER7)(Note 13)
HALT Current (Note 6)
VCC = 5.5V, CKI = 0 MHz
(SEC5)
(SER7)
IDLE Current (Note 5)
CKI = 10 MHz
VCC = 5.5V, tC = 1 µs
(SEC5)
(SER7)
Input Levels (VIH, VIL)
RESET
Logic High
Logic Low
CKI, All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis
VCC = 5.5V
VCC = 5.5V, VIN = 0V
VCC = 5.5V
VCC = 2.7V
Min Typ
Max
Units
2.7 5.5 V
10
50 x 106
ns
0.1 Vcc
V
6 mA
10 mA
8 20
22
µA
µA
1.5 mA
1.5 mA
0.8 Vcc
0.7 Vcc
−2
−40
0.25 Vcc
0.31 Vcc
0.2 Vcc
0.2 Vcc
+2
−250
V
V
V
V
µA
µA
V
V
5 www.national.com
5 Page 
4.0 Pin Descriptions (Continued)
DS100973-12
FIGURE 6. I/O Port Configurations — Output Mode
DS100973-11
FIGURE 7. I/O Port Configurations — Input Mode
5.0 Functional Description
The architecture of the devices is a modified Harvard archi-
tecture. With the Harvard architecture, the program memory
ROM or EPROM is separated from the data store memory
(RAM). Program Memory will be referred to as ROM. Both
ROM and RAM have their own separate addressing space
with separate address buses. The architecture, though
based on the Harvard architecture, permits transfer of data
from ROM to RAM.
5.1 CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tC) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
S is the 8-bit Segment Address Register used to extend the
lower half of the address range (00 to 7F) into 256 data seg-
ments of 128 bytes each.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). With reset the SP is initialized to
RAM address 02F Hex (devices with 64 bytes of RAM), or
initialized to RAM address 06F Hex (devices with 128 bytes
of RAM).
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
5.2 PROGRAM MEMORY
The program memory consists of 4096 Bytes of ROM or
32,768 bytes of OTP EPROM. These bytes may hold pro-
gram instructions or constant data (data tables for the LAID
instruction, jump vectors for the JID instruction, and interrupt
vectors for the VIS instruction). The program memory is ad-
dressed by the 15-bit program counter (PC). All interrupts in
the device vector to program memory location 0FF Hex. The
contents of the program memory read 00 Hex in the erased
state. Program execution starts at location 0 after RESET.
5.3 DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
The data memory consists of 256 bytes of combined EE-
RAM and RAM. Sixteen bytes of RAM are mapped as “reg-
isters” at addresses 0F0 to 0FE Hex. These registers can be
loaded immediately, and also decremented and tested with
the DRSZ (decrement register and skip if zero) instruction.
The memory pointer registers X, SP and B are memory
mapped into this space at address locations 0FC to 0FE Hex
respectively, with the other registers (except 0FF) being
available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
5.4 EERAM / NON-VOLATILE MEMORY
The devices provide 128 bytes of EERAM in segment 1 for
nonvolatile data memory. The data EERAM can be read and
written in exactly the same way as the RAM. All instructions
that perform read and write operations on the RAM work
similarly upon the data EERAM. EERAM write cycles take
much more time than reads. During this time, processing
continues, but all EERAM accesses are inhibited. The data
EERAM contains all 00s when shipped by the factory.
A data memory EERAM programming cycle is initiated by an
instruction that writes to the EERAM such as X, LD, SBIT
and RBIT. The EERAM memory support circuitry sets the
E2BUSY flag in the E2CFG register immediately upon begin-
ning a data EERAM write cycle. It will be automatically reset
by the hardware at the end of the data EERAM write cycle.
The application program should test the E2BUSY flag before
attempting a read or write operation to the data EERAM. An
EERAM read or write operation while an operation is in
progress will be ignored and the E2ILRW flag in the E2CFG
register will be set to indicate the error status. Once the write
operation starts, nothing will stop the write operation, not by
resetting the device, and not even turning off the VCC will
guarantee the write operation to stop.
11 www.national.com
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