PDF ADF4355-3 Data sheet ( Hoja de datos )

Número de pieza	ADF4355-3
Descripción	Microwave Wideband Synthesizer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Microwave Wideband Synthesizer with Integrated VCO ADF4355-3 FEATURES GENERAL DESCRIPTION RF output frequency range: 51.5625 MHz to 6600 MHz The ADF4355-3 allows the implementation of fractional-N or Fractional-N synthesizer and integer-N synthesizer integer-N phase-locked loop (PLL) frequency synthesizers when High resolution 38-bit modulus used with an external loop filter and an external reference Low phase noise, voltage controlled oscillator (VCO) frequency. A series of frequency dividers at the output provide Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output operation from 51.5625 MHz to 6600 MHz. All power supplies: 3.3 V Logic compatibility: 1.8 V Programmable dual modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect The ADF4355-3 has an integrated VCO with a fundamental output frequency ranging from 3300 MHz to 6600 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 51.5625 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable. APPLICATIONS Control of all on-chip registers is through a simple 3-wire interface. Wireless infrastructure (W-CDMA, TD-SCDMA, The ADF4355-3 operates with analog, digital, charge pump, and WiMAX, GSM, PCS, DCS, DECT) VCO power supplies ranging from 3.1515 V to 3.4485 V. The Point to point/point to multipoint microwave links ADF4355-3 also contains hardware and software power-down Satellites/VSATs modes. Test equipment/instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM CE AVDD DVDD VP RSET VVCO VRF AVDD REF IN A REFIN B CLK DATA LE ×2 DOUBLER 10-BIT R COUNTER ÷2 DIVIDER DATA REGISTER FUNCTION LATCH INTEGER REG FRACTION MODULUS REG REG THIRD-ORDER FRACTIONAL INTERPOLATOR LOCK DETECT MULTIPLEXER CHARGE PUMP PHASE COMPARATOR VCO CORE ÷116/2//342//864 OUTPUT STAGE MUXOUT CREG1 CREG2 CPOUT VTUNE VREF VBIAS VREGVCO RFOUTA+ RFOUTA– N COUNTER MULTIPLEXER OUTPUT STAGE PDBRF RFOUTB+ RFOUTB– ADF4355-3 AGND CPGND AGNDRF Figure 1. SDGND AGNDVCO Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ADF4355-3 TIMING CHARACTERISTICS AVDD = DVDD =VRF = VP = VVCO = 3.3 V ± 4.5%, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Write Timing Parameter Limit fCLK 50 t1 10 t2 5 t3 5 t4 10 t5 10 t6 5 t7 20 or (2/fPFD), whichever is longer Unit MHz max ns min ns min ns min ns min ns min ns min ns min Description SPI CLK frequency LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Write Timing Diagram CLK t4 t5 DATA DB31 (MSB) LE t1 t2 t3 DB30 DB3 (CONTROL BIT C4) DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) Figure 2. Write Timing Diagram DB0 (LSB) (CONTROL BIT C1) t7 t6 Rev. A \| Page 5 of 34 5 Page Data Sheet –80 –90 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 16. Spur Performance, RFOUTA+ = 2.591 GHz, REFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide-by-2 Selected, Loop Filter Bandwidth = 35 kHz, Channel Spacing = 20 kHz ADF4355-3 5 4 3 2 1 0 –1 –2 –3 –4 –5 –150 0 150 300 450 600 750 900 1050 1200 1350 TIME (µs) Figure 17. Lock Time for 100 MHz Jump from 3300 MHz to 6600 MHz, Loop Bandwidth = 3 kHz Rev. A \| Page 11 of 34 11 Page

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