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PDF PE43601 Data sheet ( Hoja de datos )
| Número de pieza | PE43601 | |
| Descripción | RF Digital Attenuator | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
The PE43601 is a HaRP™-enhanced, high linearity, 6-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 15.75 dB attenuation range in 0.25 dB steps. The
Peregrine 50Ω RF DSA provides a serial-addressable CMOS
control interface. It maintains high attenuation accuracy over
frequency and temperature and exhibits very low insertion loss
and low power consumption. Performance does not change
with VDD due to on-board regulator. This next generation
Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint.
The PE43601 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Package Type
32-lead 5x5x0.85 mm QFN Package
Product Specification
PE43601
50 Ω RF Digital Attenuator
6-bit, 15.75 dB, 9 kHz - 6.0 GHz
Features
• HaRP™-enhanced UltraCMOS™ device
• Attenuation: 0.25 dB steps to 15.75 dB
• High Linearity: Typical +58 dBm IIP3
• Excellent low-frequency performance
• 3.3 V or 5.0 V Power Supply Voltage
• Fast switch settling time
• Programming Modes:
• Direct Parallel
• Latched Parallel
• Serial-Addressable: Program up to
eight addresses 000 - 111
• Serial Two-Byte Protocol: Address and
Data Word
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
• No DC blocking capacitors required
• Packaged in a 32-lead 5x5x0.85 mm QFN
Figure 2. Functional Schematic Diagram
RF Input
Switched Attenuator Array
RF Output
Parallel Control 6
Serial In
CLK
LE
Control Logic Interface
A0 A1
Document No. 70-0253-05 │ www.psemi.com
A2
P/S
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
1 page  
PE43601
Product Specification
Figure 18. Pin Configuration (Top View)
NC
VDD
P/S
A0
GND
GND
RF1
GND
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
Exposed
Solder pad
9 10 11 12 13 14 15 16
24 CLK
23 LE
22 A1
21 A2
20 GND
19 GND
18 RF2
17 GND
Table 2. Pin Descriptions
Pin No. Pin Name
Description
1 N/C No Connect
2 VDD Power supply pin
3 P/̅ S Serial/Parallel mode select
4 A0 Address bit A0 connection
5, 6, 8 - 17,
19, 20, 26
GND
Ground
7 RF1 RF1 port
18 RF2 RF2 port
21 A2 Address bit A2 connection
22 A1 Address bit A1 connection
23 LE Serial interface Latch Enable input
24
CLK
Serial interface Clock input
25 SI Serial interface Data input
27 C8 (D5) Parallel control bit, 8 dB
28 C4 (D4) Parallel control bit, 4 dB
29 C2 (D3) Parallel control bit, 2 dB
30 C1 (D2) Parallel control bit, 1 dB
31 C0.5 (D1) Parallel control bit, 0.5 dB
32 C0.25 (D0) Parallel control bit, 0.25 dB
Paddle
GND
Ground for proper operation
Note: Ground C0.25, C0.5, C1 C2, C4, C8 if not in use.
Document No. 70-0253-05 │ www.psemi.com
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43601 in
the 32-lead 5x5 QFN package is MSL1.
Switching Frequency
The PE43601 has a maximum 25 kHz switching rate.
Switching rate is defined to be the speed at which the
DSA can be toggled across attenuation states.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 13
5 Page 
PE43601
Product Specification
Figure 23. Evaluation Board Schematic
Peregrine Specification 102-0381
VDD
_
P/S D0
D1
D2 D3 D4 D5 D6
J1
HEADER 14
22
44
66
88
10 10
12 12
14 14
11
33
55
77
99
11 11
13 13
D0
D1
D2
D3
D4
D5
D6
J3
CON2
1
2
VDD
C6
100pF
C5 C3
100pF
C4
100pF
C2
100pF
100pF
C1
100pF
C0
100pF
C9
0.1µF
C10
100pF
C8
100pF
C13
100pF
C14
100pF
J6
SMA
De-embeding trace
Z=50 Ohm
1
J7
SMA
1
J4
SMA
1
Z=50 Ohm
VDD
_
P/S
A0
1
GND
2 VDD
CLK 24
LE 23
3 PS
A1 22
4 A0
U1 A2 21
PE43XOX DSA 50 OHM 5X5 MLPQ32
5 GND
VSS 20
6 GND
GND 19
7 RF1
8 GND
RF2 18
GND 17
A1
A2
CLK
SI
LE
SERIAL
HEADER 4
1 CLOCK
2 SI
3 LE
4 GND
VDD
A0_2
A1_2
A2_2
ADD
A0 VDD
A1 VDD
A2 VDD
A2_1
A1_1
A0_1
HEADER3X3
Z=50 Ohm
R1
0 OHM
R2
J5
SMA
1
0 OHM
C11
0.1uF
C12
100pf
VSS
J2
1
2
CON2
Figure 24. Package Drawing
Note: Pin 26 is grounded. On the PE43601 pin 20 (shown as
VSS) must also be grounded.
QFN 5x5 mm
MAX
A NOM
0.900
0.850
MIN 0.800
Document No. 70-0253-05 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PE43601.PDF ] | |
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