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PE42451 데이터시트 PDF




Peregrine Semiconductor에서 제조한 전자 부품 PE42451은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 PE42451 자료 제공

부품번호 PE42451 기능
기능 High-Isolation RF Switch
제조업체 Peregrine Semiconductor
로고 Peregrine Semiconductor 로고


PE42451 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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PE42451 데이터시트, 핀배열, 회로
Product Description
The PE42451 is a HaRP™-enhanced Absorptive SP5T
RF Switch developed on the UltraCMOS® process
technology. This general purpose switch is comprised of
five symmetric RF ports and has very high isolation. An
on-chip CMOS decode logic facilitates a three-pin low
voltage CMOS control interface and an optional external
Vss feature (VssEXT). High ESD tolerance and no
blocking capacitor requirements make this the ultimate in
integration and ruggedness.
Peregrine’s HaRP™ technology enhancements deliver
high linearity and exceptional harmonics performance. It
is an innovative feature of the UltraCMOS® process,
providing performance superior to GaAs with the
economy and integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
RF5
ESD
50
RF4
ESD
50
CMOS Control/
Driver and ESD
ESD
50
ESD
50
ESD
50
RF1
RF2
RF3
V1 V2 V3 VDD VssEXT (optional)
DOC-02114
Product Specification
PE42451
SP5T Absorptive UltraCMOS®
High-Isolation RF Switch
450-4000 MHz, VssEXT option
Features
 HaRP™-enhanced UltraCMOS® device
 Five symmetric, absorptive RF ports
 High Isolation:
 68 dB at 450 MHz
 62 dB at 900 MHz
 55 dB at 2100 MHz
 53 dB at 2600 MHz
 50 dB at 4000 MHz
 IIP2 of 95 dBm, IIP3 of 58 dBm
 High ESD tolerance of 3500 V HBM
 Optional External Vss Control (VssEXT)
 Three pin CMOS logic control
 No blocking capacitors required
 Small RoHS-Compliant 24-lead 4x4 mm
QFN package
Figure 2. Package Photo
24-lead 4x4 mm QFN
Document No. DOC-22914-2 www.psemi.com
©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11




PE42451 pdf, 반도체, 판매, 대치품
Evaluation Kit
The SP5T switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42451. The RF
common port is connected through a 50 transmission
line via the top SMA connector. RF1, RF2, RF3 and
RF4 are connected through 50 transmission lines via
side SMA connectors. A through 50 transmission is
available via SMA connectors RFCAL1 and RFCAL2.
This transmission line can be used to estimate the loss
of the PCB over the environmental conditions being
evaluated.
The EVK board is constructed with four metal layers on
dielectric materials of Rogers 4003C and 4450 with a
total thickness of 32 mils. Layer 1 and layer 3 provide
ground for the 50 ohm transmission lines. The 50 ohm
transmission lines are designed in layer 2 for high
isolation purpose and use a stripline waveguide design
with a trace width of 9.4 mils and trace metal thickness
of 1.8 mils. The board stack up for 50 ohm transmission
lines has 8 mil thickness of Rogers 4003C between
layer 1 and layer 2, and 10 mil thickness of Rogers
4450 between layer 2 and layer 3. Please consult
manufacturer's guidelines for proper board material
properties in your application. The PCB should be
designed in such a way that RF transmission lines and
sensitive DC i/o traces such as VssEXT are heavily
isolated from one another, otherwise the true
performance of the PE42451 will not be yielded.
PE42451
Product Specification
Figure 4. Evaluation Board Layouts
Peregrine Specification PRT-50444
Figure 5. Evaluation Board Schematic
Peregrine Specification DOC-44837
R1
0 OHM
C1
DNI
R3
0 OHM
C2
100pF
RFC
2
R5
0 OHM
C3
100pF
R2
1M
R4
1M
R6
1M
RF5 1
RF5
RF4 1
RF4
1 GND
2 RF5
3 GND
4 GND
5 RF4
6 GND
U1
PE4245x_24L_QFN
V2 18
V1 17
VDD 16
GND 15
RF1 14
GND 13
RF1
RF1
1
R7
0 OHM
C4
100pF
R9
0 OHM
C5
100pF
R8
1M
C6
1µF
RF3 1
RF3 RF2
RF2
1
RFCAL1
1 RF
RF CAL
STRIPLINE
RFCAL2
1
©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
VSS
VDD
V3
V2
V1
J1
HEADER 14
13 13
11 11
99
77
55
33
11
14 14
12 12
10 10
88
66
44
22
USE PCB 101-0479-03
Document No. DOC-22914-2 UltraCMOS® RFIC Solutions

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PE42451 전자부품, 판매, 대치품
PE42451
Product Specification
Performance Plots @ 25 °C and 3.0 V unless otherwise specified (Continued)
Figure 13. Return Loss at active port @ 25 °C
Figure 14. Return Loss at active port @ 3.0 V
Figure 15. Return Loss: RFC @ 25 °C
Figure 16. Return Loss: RFC @ 3.0 V
Figure 17. Return Loss: All Paths, Terminated
Document No. DOC-22914-2 www.psemi.com
©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
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